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aboard_epsilon
06-08-2005, 06:07 PM
My computer has a problem
when I shut it down it cant be restarted powered-up until about 10 hours have elapsed.
this happens even after the comp is cold and its shut down.
the comp is not overheating ......and appears to run faultlessly for any period of time until shutdown.
the only thing i can think of is some sort of virus is causing this
anyone got any ideas .........
I've updated Norton and it is scanning now .
if you dont hear or see from me for a while ..you will know That its packed up completly.
also power supply has began making strange noices ...so maybe it's that ......fan on power supply is clean
but this time lapse says something else to me .
all the best.mark

Evan
06-08-2005, 06:09 PM
Although you might well have a virus that isn't what is causing the problem. Best guess is that the power supply is failing.

jfsmith
06-08-2005, 06:26 PM
My "Future Father In Law" had this same problem, I replaced the power supply and everything is fine, it's the power supply most likely, like Evan said.

Jerry

aboard_epsilon
06-08-2005, 06:27 PM
ok thanks for the quick answer Evan.
now then...
Is a power supply universal.
do the conectors fit all.
my current one is a Chieftec HPC-360-202.
will all the conections be the same.
my comp is running an asus A7N8X DELUXE.
Athlon xp-3000+
Two hard drives, dvd/rewiter plus cd rom
I'm currently looking at buying one of these.
someone here advised these ones a few weeks ago ..when i reported these strange noices.

http://www.overclockers.co.uk/acatalog/Online_Catalogue_Q_Tec_139.html

it says it has short leads .i will measure tommorrow.
will i gane any advantage in reliabilty in going up on the wattage.
All the best..mark

Evan
06-08-2005, 06:47 PM
A standard ATX 450 watt supply will do fine. You can go cheap or you can go good for about twice the price. I sell both since some people only care about price. For example a cheap 350 watt supply weighs about a pound. The same supply in a quality brand like Crystal Power weighs about 2.5 pounds. The difference in weight is the heat sinks, massive heat sinks.

If it is a quality supply then 400 watts will be fine.

[This message has been edited by Evan (edited 06-08-2005).]

3 Phase Lightbulb
06-08-2005, 07:05 PM
It sounds like you could use another power supply if the one you have now is humming, but I doubt a new power supply is going to fix your problem.

The A7N8X has a nVidia chipset which uses the CMOS battery to power the nVidia master reset logic. A low CMOS battery will prevent the motherboard from powering up. When you turn off your system, the CMOS battery probably doesn't have enough voltage or current for the reset logic. After you wait 10+ hours, there is probably just enough to power it back up.

Get a new power supply so your humming one won't piss you off later, but also get a new CMOS battery to fix the "cant be restarted powered-up until about 10 hours have elapsed.
" problem.

-Adrian

aboard_epsilon
06-08-2005, 07:25 PM
yep the battery stopped keeping the clock timed a long time ago....had to set the comp to update the time off the internet at 30 min intervals to keep it on track.
think you have hit the nail on the head there Adrian.
thanks
all the best.mark

J Tiers
06-08-2005, 11:07 PM
Might be battery, but while you are waiting actually is when the battery is draining. Should NOT be draining when on.

If its low, you'd think it would work best when the load has been off it, like right after it was turned off.....

If the lights won't come on, and no fan noise, most likely power supply has a problem.

3 Phase Lightbulb
06-09-2005, 12:29 AM
<font face="Verdana, Arial" size="2">Originally posted by J Tiers:
Might be battery, but while you are waiting actually is when the battery is draining. Should NOT be draining when on.

If its low, you'd think it would work best when the load has been off it, like right after it was turned off.....

If the lights won't come on, and no fan noise, most likely power supply has a problem.

</font>


That's not how the RTC/NVRAM/CMOS works. The RTC/NVRAM is kept alive with a CMOS Oscillator. As you know, the current consumption of CMOS gate is proportional to switching frequency. Once the battery voltage drops below the CMOS N-type level, the oscillator will stop switching and there will be zero current being drawn from the battery.

When the computer is turned on, there is a massive load on the CMOS battery to power the reset logic. The 10+ hour rest helps provide this.

Once the computer is on, the CMOS low dropout regulator will trip and power the RTC/NVRAM but since the battery is below the dropout voltage, it's now drawing current through the decoupling cap that is tied to ground. The battery is now trying to charge the decoupling cap that is slowly leaking to ground.

-Adrian

J Tiers
06-09-2005, 08:42 AM
<font face="Verdana, Arial" size="2">Originally posted by 3 Phase Lightbulb:

That's not how the RTC/NVRAM/CMOS works. The RTC/NVRAM is kept alive with a CMOS Oscillator. As you know, the current consumption of CMOS gate is proportional to switching frequency. Once the battery voltage drops below the CMOS N-type level, the oscillator will stop switching and there will be zero current being drawn from the battery.

When the computer is turned on, there is a massive load on the CMOS battery to power the reset logic. The 10+ hour rest helps provide this.

Once the computer is on, the CMOS low dropout regulator will trip and power the RTC/NVRAM but since the battery is below the dropout voltage, it's now drawing current through the decoupling cap that is tied to ground. The battery is now trying to charge the decoupling cap that is slowly leaking to ground.

-Adrian</font>


It is my understanding that in every case, the battery is a BACKUP, which is taken off-line when the power supply is on....

BUT, when the computer supply is off, the BATTERY must supply the clock etc. However small the drain, it is there, and it is there when power is OFF.

The CAPACITOR, first of all, is what takes the surge (if any). Second, if the capacitor is such a major drain, it is draining 24/7/365, not JUST when the computer is off.

And any designer who lets the cap leakage be such a huge factor in the deal has done a really poor job.

Finally, for years, my computers have had flash memory (NVRAM, or "non-volatile ram") for their setup, bios, etc. I believe it is now cheaper in any case. Flash requires no battery nor clock to maintain it. The RTC does.

And if the RTC stops when computer is off, you computer clock will be wrong....it isn't...... draw your own conclusions.

In any case, if teh machine makes no noise and lights no lights, the power supply failed to come up.

If the CMOS were the only problem, the PS would make noise, but the computer would be dead.

[This message has been edited by J Tiers (edited 06-09-2005).]

aboard_epsilon
06-09-2005, 09:43 AM
well i replaced the battery with a new one .
same problem....
so i went out and bought a new power supply ...dead easy to install..was amazzzzzed
now everything is A-OK
Thanks guys.
all the best.mark

3 Phase Lightbulb
06-09-2005, 11:59 AM
<font face="Verdana, Arial" size="2">Originally posted by J Tiers:

It is my understanding that in every case, the battery is a BACKUP, which is taken off-line when the power supply is on....

BUT, when the computer supply is off, the BATTERY must supply the clock etc. However small the drain, it is there, and it is there when power is OFF.</font>

Yes, the battery is a backup, but only when it's voltage is above a certain level. Once it drops below a certain voltage, it stops running the CMOS RTC/NVRAM oscillator and the NVRAM contents start to decay.


<font face="Verdana, Arial" size="2">Originally posted by J Tiers:
The CAPACITOR, first of all, is what takes the surge (if any). Second, if the capacitor is such a major drain, it is draining 24/7/365, not JUST when the computer is off.

And any designer who lets the cap leakage be such a huge factor in the deal has done a really poor job.</font>

As I said, this is only a problem as soon as the battery voltage drops below the voltage of the bypass/decopuling cap. It would be similar to what happens when a cell reverses.


<font face="Verdana, Arial" size="2">Originally posted by J Tiers:
Finally, for years, my computers have had flash memory (NVRAM, or "non-volatile ram") for their setup, bios, etc. I believe it is now cheaper in any case. Flash requires no battery nor clock to maintain it. The RTC does.</font>

Flash is __NOT__ NVRAM. Flash is a form of EEPROM technology with a limited number of write cycles. NVRAM is non-volatile SRAM with an unlimited number of write cycles. They are two completely different technologies used for two completely different things. The RTC/NVRAM is actually one tightly coupled unit. The RTC writes the Time/Date into the dual-ported NVRAM every second to the first 16 bytes of NVRAM. The rest of the NVRAM is used for BIOS congiration. The BIOS itself is either stored in PROM, EPROM, or Flash.


Mark - Sometimes when you replace the CMOS battery, you need to clear/reset the NVRAM with a jumper, or wait for the NVRAM to completely decay over time. It still sounds like the battery was the problem (Swapping out a bad battery with a good battery but still having incorrect/half baked NVRAM settings) can prevent some Chipsets from asserting the Power signal to the Power supply. I think what happened is when you replaced the power supply, you unplugged it from the wall so the 5v standy voltage that normally is always there dropped causing your NVRAM to decay much faster. So in effect, you shorted the 10+ hour decay time to seconds by unplugging the power supply from the wall (even though it's off, it can still supply 5v standby).

-Adrian

Evan
06-09-2005, 12:38 PM
The main problem with the power supplies is gradual failure of the electrolytic caps. High ripple currents combined with electrolyte dry-out result in microscopic defects in the oxide layer resulting in reduced capacitance. The oxide film is self repairing when the stress is removed from the plates. This ability to self repair diminishes as the capacitor ages. When it is close to failure it takes minutes or hours instead of milliseconds. After operation under full running stress the capacitance becomes noticably reduced which causes excess ripple on supply outputs. There is a standby 5volt supply through pin 9 on the power connector used for the WOL and power on circuit in an ATX system. This is supplied separately from the other supply voltages and is always on.

If the supply has just been operating and is turned off an attempt to restart it may result in the criteria for voltage regulation within the supply to fail. In turn, the supply will not supply the required "power good" signal to the motherboard and the system will not turn on. The power good signal fails if the regulation criteria are not met within a specified period of time within the supply.

After a period of "rest" the electrolytic capacitors will "self repair" and the next time a turn on is attempted the power good criteria will be met, just barely. Once power good is asserted the mother board power controller asserts "power on" to the supply through pin 14. At this time the excess ripple in the supply is smoothed by the bypass capacitors on the motherboard so operation continues and the computer turns on.

aboard_epsilon
06-09-2005, 12:50 PM
when i had the problems
one of the things i was doing was unpluging it from the wall in an effort to get the thing running
the times it did start after 10 hours it had been unpluged .because i was aware that the power supply was warm even with the computer shut down
and was trying everything out .
all this before the new batt or the power supply.
now i have another problem
the clock will not update itself
says:-
"an error occored getting the status of your last snycronization. the rpc server is unavalble"
whewn i try both
time.windows.com
and
time.nist.gov
my brother lives 1 mile away he has the same server as me and his updates each and every time.
mine does not even look on the net ..the two little monitors do not light up...when i press update .
there again.....when i took the battery out the bios is now in default mode ....so i will have to correct that when i get chance.
also have this add-watch .this may be blocking it .......its stops things getting into the registry...so maybe next time i boot up maybe it will ask if the time.windows can be blocked or allowed..i dont know .
all the best.mark

Evan
06-09-2005, 01:03 PM
Use timelord.uregina.ca

aboard_epsilon
06-09-2005, 01:09 PM
just tried...timelord.uregina.ca... same error message retuirned.
all the best.mark

3 Phase Lightbulb
06-09-2005, 01:31 PM
<font face="Verdana, Arial" size="2">Originally posted by Evan:
Once power good is asserted the mother board power controller asserts "power on" to the supply through pin 14. At this time the excess ripple in the supply is smoothed by the bypass capacitors on the motherboard so operation continues and the computer turns on.</font>

That's not how the PS_ON# (Power On) and PWR_OK (Power Ok) signals work. The motherboard asserts PS_ON# by driving it low, which causes the Power supply to turn on the +12vdc/+5vdc/[+3vdx] power rails. The motherboard now has an inrush of current and voltage but all __logic__ is held in reset until PWR_OK is asserted high from the ATX power supply. PWR_OK is tied to the Chipsets Reset fanout logic. Hard Disks, Fans, and other devices power up regardless if PWR_OK is being asserted by the power supply.

-Adrian

Evan
06-09-2005, 01:41 PM
Disable any firewall for the moment and any other filter software you have. Then try uregina again. If it works then you have a config problem with the software.

If that doesn't work then try the IP address instead of the domain name. Use 142.3.100.15

If that then works then open a dos box using the XP run command. Put in cmd and hit ok.

Then at the prompt enter
ipconfig /flushdns

Then try it with the domain name again.

If that doesn't work the search windows for a file called hosts

Just plain hosts, no extension. Open it with notepad and look for entries that refer to the time servers. Delete them and save the file. Try it again.

Evan
06-09-2005, 01:56 PM
Adrian,

Yes, I have the order reversed. But the failure mode of the supply is correct. I have seen it many times in the last 25 years since they started using switch mode supplies in various equipment.

aboard_epsilon
06-09-2005, 02:09 PM
success http://bbs.homeshopmachinist.net//smile.gif
tried all the things you mentioned Even....nothing worked
so I shut down .restarted.
put in 142.3.100.15
and only then,did it update
thanks
all the best.mark

[This message has been edited by aboard_epsilon (edited 06-09-2005).]

J Tiers
06-09-2005, 04:08 PM
<font face="Verdana, Arial" size="2">Originally posted by 3 Phase Lightbulb:
[ Flash is a form of EEPROM technology with a limited number of write cycles. [/B]</font>

Used to be..... not any more. I do remember when it was 100 cycles or so.

Flash these days has hundreds of thousands of write cycles, or more.

It is used in some "solid state hard drives", because of that.

In any case, it wasn't his CMOS battery, it was the PS, as we expected.



[This message has been edited by J Tiers (edited 06-09-2005).]

3 Phase Lightbulb
06-09-2005, 05:27 PM
<font face="Verdana, Arial" size="2">Originally posted by J Tiers:
Used to be..... not any more. I do remember when it was 100 cycles or so.

Flash these days has hundreds of thousands of write cycles, or more.

It is used in some "solid state hard drives", because of that.</font>

Flash was was never "100 cycles or so". Intel introduced flash in 1988 and the first samples available were 10,000 erase/write cycles. Today, it's still severely limited to 1,000,000 cycles. Not much has changed except density. Flash and NVRAM are completely different technologies and not the same as you throught earlier.

Compact flash, and other storage devices that use Flash memory implement wear leveling to avoid reusing the same low level flash blocks over and over even though the high level file system might keep writing data to the same "Sector".

It only takes a few seconds to render a flash block unreliable.


<font face="Verdana, Arial" size="2">Originally posted by J Tiers:

In any case, it wasn't his CMOS battery, it was the PS, as we expected.

[This message has been edited by J Tiers (edited 06-09-2005).]</font>

I think it was a combination of the NVRAM contents and the CMOS battery level. There are a lot of motherboards out there that won't even assert the PS_ON# signal if the contents of NVRAM are corrupt. Some motherboards will only boot with a valid NVRAM configuration, or a cleared NVRAM configuration. Some motherboards will boot with an invalid NVRAM configuration but will display a NVRAM checksum error. The only way to find out is with more testing with the new CMOS battery and the original power supply.

-Adrian

aboard_epsilon
06-09-2005, 06:52 PM
if its any help i put a multimetre on the old battery
was showing 2.99 volts
new battery read 3.3 volts.
all the best.mark

3 Phase Lightbulb
06-09-2005, 06:57 PM
You need to measure it under load over a period of time otherwise the voltage reading doesn't really say much. If your CMOS clock did not retain the date/time then it's probably low enough to let NVRAM settings decay as well. You can unplug the battery and sometimes it still takes awhile before NVRAM completely decays.

Sometimes you actually have to install a jumper on the motherboard to reset the NVRAM settings. Some motherboards use NVRAM data to set clock frequency, clock polarity, local bus frequency, CPU voltage selects, etc. Some motherboards won't even assert the PS_ON# with invalid NVRAM settings. Usually those are the types of motherboards that have jumperless configuration for different CPU types/speeds/voltages/bus frequences/SDRAM configurations/etc. A zeroed out NVRAM is a "safemode".

-Adrian


[This message has been edited by 3 Phase Lightbulb (edited 06-09-2005).]

mochinist
06-09-2005, 08:42 PM
1 Introduction

Consistent hashing must work. We leave out these algorithms due to resource constraints. To put this in perspective, consider the fact that seminal biologists regularly use hierarchical databases to achieve this mission. Here, we disprove the refinement of consistent hashing [16,16,11]. The study of virtual machines would greatly improve the investigation of kernels.

Mina, our new methodology for embedded epistemologies, is the solution to all of these challenges. Though conventional wisdom states that this issue is largely overcame by the evaluation of multi-processors, we believe that a different solution is necessary. For example, many heuristics explore the simulation of B-trees. As a result, we concentrate our efforts on disproving that the much-touted permutable algorithm for the study of linked lists [31] is in Co-NP.

This work presents two advances above previous work. We show that replication and I/O automata can agree to address this obstacle. Our intent here is to set the record straight. We concentrate our efforts on validating that lambda calculus and information retrieval systems can interact to accomplish this mission.

We proceed as follows. For starters, we motivate the need for spreadsheets. We show the improvement of forward-error correction. To overcome this obstacle, we show that the foremost atomic algorithm for the refinement of erasure coding by Lee and Miller is impossible. Next, we place our work in context with the previous work in this area. In the end, we conclude.

2 Wireless Information

Motivated by the need for gigabit switches, we now introduce a framework for confirming that context-free grammar and fiber-optic cables are entirely incompatible [22]. We show Mina's concurrent management in Figure 1. This may or may not actually hold in reality. Our approach does not require such a robust allowance to run correctly, but it doesn't hurt. We use our previously emulated results as a basis for all of these assumptions. Despite the fact that system administrators generally postulate the exact opposite, Mina depends on this property for correct behavior.


dia0.png
Figure 1: The diagram used by our application.

Our solution does not require such a natural location to run correctly, but it doesn't hurt [26,29,15]. Consider the early framework by Takahashi; our model is similar, but will actually solve this obstacle. Although futurists usually assume the exact opposite, our framework depends on this property for correct behavior. The question is, will Mina satisfy all of these assumptions? Exactly so. This at first glance seems unexpected but often conflicts with the need to provide the Turing machine to theorists.

3 Implementation

After several months of onerous coding, we finally have a working implementation of our heuristic. Mina is composed of a centralized logging facility, a centralized logging facility, and a hacked operating system. The client-side library and the hacked operating system must run on the same node. The homegrown database and the server daemon must run on the same node.

4 Results and Analysis

Building a system as experimental as our would be for not without a generous performance analysis. We did not take any shortcuts here. Our overall evaluation seeks to prove three hypotheses: (1) that flash-memory speed behaves fundamentally differently on our mobile telephones; (2) that the lookaside buffer has actually shown duplicated hit ratio over time; and finally (3) that we can do little to toggle a method's RAM speed. The reason for this is that studies have shown that 10th-percentile energy is roughly 48% higher than we might expect [14]. Our evaluation strives to make these points clear.

4.1 Hardware and Software Configuration


figure0.png
Figure 2: The effective response time of Mina, compared with the other systems.

We modified our standard hardware as follows: we performed an emulation on the KGB's XBox network to measure I. Sato's deployment of redundancy in 1970. To find the required tape drives, we combed eBay and tag sales. For starters, we added some 200MHz Intel 386s to our decommissioned Apple ][es. Second, we removed more CPUs from our decommissioned UNIVACs. Third, we removed 100MB of ROM from our trainable testbed. We only noted these results when simulating it in middleware. Continuing with this rationale, we removed 200MB of NV-RAM from our network. This is an important point to understand. In the end, we quadrupled the USB key speed of our network to consider the median sampling rate of DARPA's mobile telephones.


figure1.png
Figure 3: The 10th-percentile response time of Mina, compared with the other methodologies.

Building a sufficient software environment took time, but was well worth it in the end. Our experiments soon proved that making autonomous our separated power strips was more effective than instrumenting them, as previous work suggested. We added support for Mina as a discrete embedded application. Second, we note that other researchers have tried and failed to enable this functionality.


figure2.png
Figure 4: The effective throughput of our heuristic, as a function of clock speed.

4.2 Experiments and Results


figure3.png
Figure 5: The expected bandwidth of our application, as a function of distance.

Is it possible to justify the great pains we took in our implementation? Exactly so. That being said, we ran four novel experiments: (1) we measured flash-memory throughput as a function of USB key throughput on a LISP machine; (2) we measured E-mail and database performance on our mobile telephones; (3) we ran access points on 98 nodes spread throughout the Internet network, and compared them against 802.11 mesh networks running locally; and (4) we deployed 77 PDP 11s across the Internet-2 network, and tested our multicast heuristics accordingly [1]. We discarded the results of some earlier experiments, notably when we measured RAID array and WHOIS throughput on our underwater cluster.

Now for the climactic analysis of experiments (1) and (3) enumerated above. Such a hypothesis at first glance seems counterintuitive but fell in line with our expectations. Gaussian electromagnetic disturbances in our millenium testbed caused unstable experimental results. Continuing with this rationale, we scarcely anticipated how accurate our results were in this phase of the evaluation methodology. Third, note how deploying Lamport clocks rather than deploying them in the wild produce smoother, more reproducible results.

We next turn to all four experiments, shown in Figure 2. The key to Figure 5 is closing the feedback loop; Figure 5 shows how Mina's effective USB key speed does not converge otherwise. The key to Figure 5 is closing the feedback loop; Figure 2 shows how our methodology's NV-RAM space does not converge otherwise. Note the heavy tail on the CDF in Figure 4, exhibiting amplified average seek time.

Lastly, we discuss experiments (3) and (4) enumerated above. Note the heavy tail on the CDF in Figure 2, exhibiting exaggerated complexity. Second, the many discontinuities in the graphs point to exaggerated expected interrupt rate introduced with our hardware upgrades. Third, the many discontinuities in the graphs point to amplified sampling rate introduced with our hardware upgrades.

5 Related Work

Our approach is related to research into telephony, heterogeneous technology, and signed symmetries [2]. It remains to be seen how valuable this research is to the machine learning community. Furthermore, Maruyama and Gupta [12,2,3,17,8,2,5] proposed the first known instance of 802.11b [32,7,23]. We plan to adopt many of the ideas from this previous work in future versions of our heuristic.

The deployment of the study of 4 bit architectures has been widely studied. In our research, we surmounted all of the obstacles inherent in the previous work. Taylor and Wilson suggested a scheme for developing the World Wide Web, but did not fully realize the implications of interactive methodologies at the time [21]. Mina is broadly related to work in the field of event-driven theory [30], but we view it from a new perspective: XML [20]. Our approach to concurrent algorithms differs from that of D. Shastri et al. as well [28,27,6].

A major source of our inspiration is early work by Ito on lossless models. John Hopcroft et al. [9,13,18] suggested a scheme for controlling SCSI disks, but did not fully realize the implications of rasterization at the time [25]. On a similar note, we had our approach in mind before Jackson et al. published the recent much-touted work on random technology. Unlike many existing solutions [4], we do not attempt to learn or enable virtual machines [1]. Unfortunately, the complexity of their method grows exponentially as extreme programming grows. The choice of Boolean logic in [10] differs from ours in that we enable only confusing communication in Mina. Although this work was published before ours, we came up with the solution first but could not publish it until now due to red tape. Our method to forward-error correction differs from that of Allen Newell et al. [24] as well [19].

6 Conclusion

In conclusion, we disproved that although suffix trees can be made large-scale, mobile, and ambimorphic, the World Wide Web and randomized algorithms can interfere to accomplish this ambition. On a similar note, Mina has set a precedent for the emulation of reinforcement learning, and we expect that theorists will construct Mina for years to come. Though this finding is rarely a natural aim, it has ample historical precedence. Furthermore, we also constructed new heterogeneous models. We presented a cooperative tool for refining SMPs (Mina), demonstrating that DNS can be made ubiquitous, highly-available, and unstable.

3 Phase Lightbulb
06-09-2005, 08:47 PM
We must have went to the same school. Here is my thesis http://bbs.homeshopmachinist.net//smile.gif

http://www.gnuxtools.com/helpme.pdf

-Adrian

aboard_epsilon
06-09-2005, 08:56 PM
boy o boy .
come on chaps... my comps fixed now.
thanks for the help....but
why go on and on .
and Adrian stop all this philosophy and use your noggin to get your ftp log-in working properly so that i can get some stuff uploaded there.
all the best.mark

mochinist
06-09-2005, 09:12 PM
<font face="Verdana, Arial" size="2">Originally posted by 3 Phase Lightbulb:

We must have went to the same school. Here is my thesis http://bbs.homeshopmachinist.net//smile.gif

http://www.gnuxtools.com/helpme.pdf

-Adrian</font>

LMAO you got me. I wish I woud have had access to that website in high school, I could just imagine the look on my teachers face.

J Tiers
06-09-2005, 11:08 PM
I am holding in my hand a flash drive that will be writeable as many times as necessary and will probably last until these computers are dust.

At 1 million write cycles, you could write every byte once an hour every hour of every day for 100 years.

I doubt I'll be interested when it finally fails. http://bbs.homeshopmachinist.net//biggrin.gif

Years ago in a product I used some flash that was only rated in the hundreds of writes. it was used for initial calibration tables, and would have been written to maybe 40 times in its life, depending on the cal schedule and repairs.

3 Phase Lightbulb
06-09-2005, 11:49 PM
<font face="Verdana, Arial" size="2">Originally posted by J Tiers:

I am holding in my hand a flash drive that will be writeable as many times as necessary and will probably last until these computers are dust.

At 1 million write cycles, you could write every byte once an hour every hour of every day for 100 years.

I doubt I'll be interested when it finally fails. http://bbs.homeshopmachinist.net//biggrin.gif</font>

Or you could write some piss simple software that kills an IDE Compact Flash drive in one day. The key is to write to every 128th sector on the drive over and over. Most flash chips have 64k or 128k blocks and a sector is 512bytes so every 128th hits a flash block boundary. The ware leveling that the IDE controller will do behind the scenes won't help much if scatter write on a 64k block granularity over and over as fast as the device accepts your 512 bytes sector writes.


<font face="Verdana, Arial" size="2">Originally posted by J Tiers:

Years ago in a product I used some flash that was only rated in the hundreds of writes. it was used for initial calibration tables, and would have been written to maybe 40 times in its life, depending on the cal schedule and repairs.</font>

The smallest flash device they make is the 28F256 which is 32k bytes (256k bits) with 10,000 write cycles. I think you were using EEPROM technology like a small Serial EEPROM/I2C EEPROM/E2PROM. The smallest is something like 32 bytes, and vary in write cycles.

-Adrian

Evan
06-10-2005, 02:41 AM
"The ware leveling that the IDE controller will do behind the scenes won't help much if scatter write on a 64k block granularity over and over as fast as the device accepts your 512 bytes sector writes. "

The latest leveling algorithms count the absolute number of writes to any block and when it exceeds a certain threshold will swap the pointers (and data) to a block that appears to be mostly "read only". It will take much more than a day.


[This message has been edited by Evan (edited 06-10-2005).]

J Tiers
06-10-2005, 08:43 AM
<font face="Verdana, Arial" size="2">
Or you could write some piss simple software that kills an IDE Compact Flash drive in one day. The key is to write to every 128th sector on the drive over and over.
</font>

But I have no idea why you would......

I suppose you could arrange to land the hard drive heads on the data, then start and stop the drive all day too.....

You can drive your car into a bridge abutment at 90 MPH, also, but that doesn't make it rational to do it.... http://bbs.homeshopmachinist.net//biggrin.gif

3 Phase Lightbulb
06-10-2005, 11:16 AM
<font face="Verdana, Arial" size="2">Originally posted by Evan:
"The ware leveling that the IDE controller will do behind the scenes won't help much if scatter write on a 64k block granularity over and over as fast as the device accepts your 512 bytes sector writes. "

The latest leveling algorithms count the absolute number of writes to any block and when it exceeds a certain threshold will swap the pointers (and data) to a block that appears to be mostly "read only". It will take much more than a day.


[This message has been edited by Evan (edited 06-10-2005).]</font>

Exactly, that's why I said you write once to every 128th sector / "block boundary" over and over. It doesn't matter what alternate block the ware leveling chooses, because they all are equally written to so that disables ware leveling (high latency). That should have been obvious.

If you write to one block over and over, you will get a lot more write cycle latency due to the ware leveling being triggered frequently. If you scatter gather the writes on block boundaries like I explained earlier, you're going to get much better write performance.

For your generic 16MB Compact flash drive with 30K write cycles and a 1MB/Second write bandwidth it takes appromixatly 1 hour to destroy:

16,777,216 (16mb) bytes on the drive. 16,777,216 (16mb) / 65,536 (64k block size) = 256 total Flash blocks that need to each be written to for one complete cycle.

With a consertive write speed of 1mb/sec, we can write one sector (512 bytes) to each block (512 bytes * 256 = 128K). So every 128K scattered writing to all 256 blocks becomes one write cycle.

(1 MB/second / 128K = 8 write cycles per second).

8 * 60 seconds = 480 cycles per minute.
480 * 60 minutes = 28,000 cycles per hour.

-Adrian

Evan
06-10-2005, 11:36 AM
Odd, I could have sworn you said IDE compact flash drive. Would you mind calculating how long it will take to trash 45 gigabytes?

You may note the product below is 5 million write cycle.

http://www.m-systems.com/Content/Products/product.asp?pid=26

[This message has been edited by Evan (edited 06-10-2005).]

3 Phase Lightbulb
06-10-2005, 12:32 PM
<font face="Verdana, Arial" size="2">Originally posted by Evan:
Odd, I could have sworn you said IDE compact flash drive.</font>

I've only been talking about IDE compact flash drives so I don't understand how you could possibly be confused.



<font face="Verdana, Arial" size="2">Originally posted by Evan:
Would you mind calculating how long it will take to trash 45 gigabytes?

You may note the product below is 5 million write cycle.

http://www.m-systems.com/Content/Products/product.asp?pid=26

[This message has been edited by Evan (edited 06-10-2005).]</font>

Sure, this is fun. 45 gig Compact Flash drive.... With a 12mb a write throughput, and a 256K flash block size:

48,318,382,080 (45gb) bytes on the drive.

48,318,382,080 (45gb) / 262,114 (256k block size) = 184,341 total Flash blocks that need to each be written to for one complete cycle.

With a consertive write speed of 12mb/sec, we can write one sector (512 bytes) to each block (512 bytes * 184,341 = 94mb). So every 94mb scattered writing to all 184,341 blocks becomes one write cycle.

(12 MB/second / 94mb = 8 seconds per cycle).

60 / 8 seconds = 7.5 cycles per minute.
7.5 * 60 = 450 cycles per hour.
450 * 24 = 10,800 cycles per day.
10,800 * 365 = 3,942,000 cycles per year.

So, for a 45gb Flash disk it would take over 1 year to hit 5,000,000 cycles.

-Adrian



[This message has been edited by 3 Phase Lightbulb (edited 06-10-2005).]

Evan
06-11-2005, 02:34 AM
That is an idealized scenario. In reality you will be creating the maximum number of discarded blocks and forcing the firmware to do the maximum number of garbage collects. This will have a serious impact on write throughput. If you don't explicitly call garbage collection it will be called by firmware when a discarded block must be erased. Old blocks are only marked as discarded until they need to be erased.

As the blocks age the ECC will begin to kick in. Depending on the flash type (NAND in the above example) it can stand at least a one bit error for every 256 bytes. Read attempts will occur numerous times as data is moved to other blocks. This will very severely degrade performance before failure further slowing the process. As a wild ass guess I think it might take several years at least before total drive failure occurs. The drive will become progressively slower and slower before it fails.

Now that I think on it, it will hit a wall long before failure where every new write will result in exceeding the write threshold causing that block to be moved to one that is n-1 the threshold.

[This message has been edited by Evan (edited 06-11-2005).]

3 Phase Lightbulb
06-11-2005, 10:58 AM
In reality, I think the advertised 5,000,000 cycles might be a marketing number. The effective write cycles would be significently higher than 5,000,000 for the average end user if 5M flash parts were actually used.

If the flash parts are actually 5M cycles per block like we assume, then I would expect marketing to come up with something like 5+ Billion write cycles because that's what an end user would most likely see.

-Adrian